/******************************************************************************
* Copyright (c) 2022 Xilinx, Inc.  All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_CPU_ID 4U


/* Definitions for PMC Microblaze */
#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 0
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000F0240000
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_DADDR_SIZE 32
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 0
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_DC_AXI_MON 0
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_DP_AXI_MON 0
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_D_LMB_MON 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FAULT_TOLERANT 1
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FREQ 320000000
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_IADDR_SIZE 32
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_IC_AXI_MON 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_INSTR_SIZE 32
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_IP_AXI_MON 0
#define XPAR_MICROBLAZE_I_AXI 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_I_LMB_MON 0
#define XPAR_MICROBLAZE_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 16
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 1
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_PVR 2
#define XPAR_MICROBLAZE_PVR_USER1 0x05
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR_BIP 1
#define XPAR_MICROBLAZE_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_TRACE 1
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_USE_DCACHE 0
#define XPAR_MICROBLAZE_USE_DIV 1
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_HW_MUL 2
#define XPAR_MICROBLAZE_USE_ICACHE 0
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 1
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 0
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1

/******************************************************************/

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ XPAR_MICROBLAZE_FREQ

/******************************************************************/

 /* Definition for PSS REF CLK FREQUENCY */
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U

#define STDIN_BASEADDRESS 0xF1920000
#define STDOUT_BASEADDRESS 0xF1920000

/******************************************************************/

/* Platform specific definitions */
#define VERSAL_PLM
#define VERSALNET_PLM
#ifndef versal
#define versal
#endif

#ifndef VERSAL_NET
#define VERSAL_NET
#endif

/* Definitions for sleep timer configuration */
#define XSLEEP_TIMER_IS_DEFAULT_TIMER


/******************************************************************/
#define XPAR_CANFD_ISPS
/* Definitions for driver CANFD */
#define XPAR_XCANFD_NUM_INSTANCES 1U

/* Definitions for peripheral PSV_CANFD_1 */
#define XPAR_PSV_CANFD_1_DEVICE_ID 0U
#define XPAR_PSV_CANFD_1_BASEADDR 0xFF070000U
#define XPAR_PSV_CANFD_1_HIGHADDR 0xFF07FFFFU
#define XPAR_PSV_CANFD_1_RX_MODE 0U
#define XPAR_PSV_CANFD_1_NUM_OF_RX_MB_BUF 48U
#define XPAR_PSV_CANFD_1_NUM_OF_TX_BUF 32U
#define XPAR_PSV_CANFD_1_CAN_CLK_FREQ_HZ 99999992U
#define XPAR_PSV_CANFD_1_IS_PL 0U

/* Canonical definitions for peripheral PSV_CANFD_1 */
#define XPAR_CANFD_0_DEVICE_ID 0U
#define XPAR_CANFD_0_BASEADDR 0xFF070000U
#define XPAR_CANFD_0_HIGHADDR 0xFF07FFFFU
#define XPAR_CANFD_0_RX_MODE 0U
#define XPAR_CANFD_0_NUM_OF_RX_MB_BUF 48U
#define XPAR_CANFD_0_NUM_OF_TX_BUF 32U
#define XPAR_CANFD_0_CAN_CLK_FREQ_HZ 99999992U
#define XPAR_CANFD_0_IS_PL 0U

/******************************************************************/
/* Definitions for driver CFRAME */
#define XPAR_XCFRAME_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_CFI_CFRAME_0 */
#define XPAR_PSV_PMC_CFI_CFRAME_0_DEVICE_ID 0
#define XPAR_PSV_PMC_CFI_CFRAME_0_BASEADDR 0xF12D0000
#define XPAR_PSV_PMC_CFI_CFRAME_0_HIGHADDR 0xF12D0FFF


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_CFI_CFRAME_0 */
#define XPAR_XCFRAME_0_DEVICE_ID XPAR_PSV_PMC_CFI_CFRAME_0_DEVICE_ID
#define XPAR_XCFRAME_0_BASEADDR 0xF12D0000
#define XPAR_XCFRAME_0_HIGHADDR 0xF12D0FFF


/******************************************************************/

/* Definitions for driver CFUPMC */
#define XPAR_XCFUPMC_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_CFU_APB_0 */
#define XPAR_PSV_PMC_CFU_APB_0_DEVICE_ID 0
#define XPAR_PSV_PMC_CFU_APB_0_BASEADDR 0xF12B0000
#define XPAR_PSV_PMC_CFU_APB_0_HIGHADDR 0xF12BFFFF


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_CFU_APB_0 */
#define XPAR_XCFUPMC_0_DEVICE_ID XPAR_PSV_PMC_CFU_APB_0_DEVICE_ID
#define XPAR_XCFUPMC_0_BASEADDR 0xF12B0000
#define XPAR_XCFUPMC_0_HIGHADDR 0xF12BFFFF


/******************************************************************/

/* Definitions for driver CSUDMA */
#define XPAR_XCSUDMA_NUM_INSTANCES 2

/* Definitions for peripheral PSV_PMC_DMA_0 */
#define XPAR_PSV_PMC_DMA_0_DEVICE_ID 0
#define XPAR_PSV_PMC_DMA_0_BASEADDR 0xF11C0000
#define XPAR_PSV_PMC_DMA_0_HIGHADDR 0xF11CFFFF
#define XPAR_PSV_PMC_DMA_0_CSUDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_PMC_DMA_1 */
#define XPAR_PSV_PMC_DMA_1_DEVICE_ID 1
#define XPAR_PSV_PMC_DMA_1_BASEADDR 0xF11D0000
#define XPAR_PSV_PMC_DMA_1_HIGHADDR 0xF11DFFFF
#define XPAR_PSV_PMC_DMA_1_CSUDMA_CLK_FREQ_HZ 0


/******************************************************************/

#define XPAR_PSV_PMC_DMA_0_DMATYPE 1
#define XPAR_PSV_PMC_DMA_1_DMATYPE 2
/* Canonical definitions for peripheral PSV_PMC_DMA_0 */
#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSV_PMC_DMA_0_DEVICE_ID
#define XPAR_XCSUDMA_0_BASEADDR 0xF11C0000
#define XPAR_XCSUDMA_0_HIGHADDR 0xF11CFFFF
#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_PMC_DMA_1 */
#define XPAR_XCSUDMA_1_DEVICE_ID XPAR_PSV_PMC_DMA_1_DEVICE_ID
#define XPAR_XCSUDMA_1_BASEADDR 0xF11D0000
#define XPAR_XCSUDMA_1_HIGHADDR 0xF11DFFFF
#define XPAR_XCSUDMA_1_CSUDMA_CLK_FREQ_HZ 0


/******************************************************************/


/* Definitions for peripheral AXI_NOC_0 */
#define XPAR_AXI_NOC_0_C0_DDR_LOW0_PMC_NOC_AXI_0_BASEADDR 0x00000000
#define XPAR_AXI_NOC_0_C0_DDR_LOW0_PMC_NOC_AXI_0_HIGHADDR 0x7FFFFFFF

/* Canonicals definitions for NOC DDR to be consumed by MMU/MPU tables in BSP*/
#define XPAR_AXI_NOC_DDR_LOW_0_BASEADDR 0x00000000
#define XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR 0x7FFFFFFF


/******************************************************************/

/* Definitions for driver EMACPS */
#define XPAR_XEMACPS_NUM_INSTANCES 2

/* Definitions for peripheral PSV_ETHERNET_0 */
#define XPAR_PSV_ETHERNET_0_DEVICE_ID 0
#define XPAR_PSV_ETHERNET_0_BASEADDR 0xFF0C0000
#define XPAR_PSV_ETHERNET_0_HIGHADDR 0xFF0CFFFF
#define XPAR_PSV_ETHERNET_0_ENET_CLK_FREQ_HZ 124999992
#define XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
#define XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 0
#define XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 40
#define XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 0
#define XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 400
#define XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 0
#define XPAR_PSV_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 249999985


/* Definitions for peripheral PSV_ETHERNET_1 */
#define XPAR_PSV_ETHERNET_1_DEVICE_ID 1
#define XPAR_PSV_ETHERNET_1_BASEADDR 0xFF0D0000
#define XPAR_PSV_ETHERNET_1_HIGHADDR 0xFF0DFFFF
#define XPAR_PSV_ETHERNET_1_ENET_CLK_FREQ_HZ 124999992
#define XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 8
#define XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 0
#define XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 40
#define XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 0
#define XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 400
#define XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 0
#define XPAR_PSV_ETHERNET_1_ENET_TSU_CLK_FREQ_HZ 249999985


/******************************************************************/

#define XPAR_PSV_ETHERNET_0_IS_CACHE_COHERENT 0
#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
#define XPAR_PSV_ETHERNET_1_IS_CACHE_COHERENT 0
#define XPAR_XEMACPS_1_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PSV_ETHERNET_0 */
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSV_ETHERNET_0_DEVICE_ID
#define XPAR_XEMACPS_0_BASEADDR 0xFF0C0000
#define XPAR_XEMACPS_0_HIGHADDR 0xFF0CFFFF
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124999992
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 0
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 40
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 0
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 400
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 0
#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249999985

/* Canonical definitions for peripheral PSV_ETHERNET_1 */
#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PSV_ETHERNET_1_DEVICE_ID
#define XPAR_XEMACPS_1_BASEADDR 0xFF0D0000
#define XPAR_XEMACPS_1_HIGHADDR 0xFF0DFFFF
#define XPAR_XEMACPS_1_ENET_CLK_FREQ_HZ 124999992
#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV0 8
#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV1 0
#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV0 40
#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV1 0
#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV0 400
#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV1 0
#define XPAR_XEMACPS_1_ENET_TSU_CLK_FREQ_HZ 249999985


/******************************************************************/


/* Peripheral Definitions for peripheral PSV_CORESIGHT_FPD_STM */
#define XPAR_PSV_CORESIGHT_FPD_STM_S_AXI_BASEADDR 0xF0B70000
#define XPAR_PSV_CORESIGHT_FPD_STM_S_AXI_HIGHADDR 0xF0B7FFFF


/* Peripheral Definitions for peripheral PSV_CRF_0 */
#define XPAR_PSV_CRF_0_S_AXI_BASEADDR 0xEC200000
#define XPAR_PSV_CRF_0_S_AXI_HIGHADDR 0xEC20FFFF


/* Peripheral Definitions for peripheral PSV_CRL_0 */
#define XPAR_PSV_CRL_0_S_AXI_BASEADDR 0xEB5E0000
#define XPAR_PSV_CRL_0_S_AXI_HIGHADDR 0xEB5EFFFF


/* Peripheral Definitions for peripheral PSV_CRP_0 */
#define XPAR_PSV_CRP_0_S_AXI_BASEADDR 0xF1260000
#define XPAR_PSV_CRP_0_S_AXI_HIGHADDR 0xF126FFFF


/* Peripheral Definitions for peripheral PSV_FPD_AFI_0 */
#define XPAR_PSV_FPD_AFI_0_S_AXI_BASEADDR 0xFD360000
#define XPAR_PSV_FPD_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF


/* Peripheral Definitions for peripheral PSV_FPD_AFI_2 */
#define XPAR_PSV_FPD_AFI_2_S_AXI_BASEADDR 0xFD380000
#define XPAR_PSV_FPD_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF


/* Peripheral Definitions for peripheral PSV_FPD_CCI_0 */
#define XPAR_PSV_FPD_CCI_0_S_AXI_BASEADDR 0xFD5E0000
#define XPAR_PSV_FPD_CCI_0_S_AXI_HIGHADDR 0xFD5EFFFF


/* Peripheral Definitions for peripheral PSV_FPD_GPV_0 */
#define XPAR_PSV_FPD_GPV_0_S_AXI_BASEADDR 0xFD700000
#define XPAR_PSV_FPD_GPV_0_S_AXI_HIGHADDR 0xFD7FFFFF


/* Peripheral Definitions for peripheral PSV_FPD_MAINCCI_0 */
#define XPAR_PSV_FPD_MAINCCI_0_S_AXI_BASEADDR 0xFD000000
#define XPAR_PSV_FPD_MAINCCI_0_S_AXI_HIGHADDR 0xFD0FFFFF


/* Peripheral Definitions for peripheral PSV_FPD_SLAVE_XMPU_0 */
#define XPAR_PSV_FPD_SLAVE_XMPU_0_S_AXI_BASEADDR 0xFD390000
#define XPAR_PSV_FPD_SLAVE_XMPU_0_S_AXI_HIGHADDR 0xFD39FFFF


/* Peripheral Definitions for peripheral PSV_FPD_SLCR_0 */
#define XPAR_PSV_FPD_SLCR_0_S_AXI_BASEADDR 0xFD610000
#define XPAR_PSV_FPD_SLCR_0_S_AXI_HIGHADDR 0xFD61FFFF


/* Peripheral Definitions for peripheral PSV_FPD_SLCR_SECURE_0 */
#define XPAR_PSV_FPD_SLCR_SECURE_0_S_AXI_BASEADDR 0xFD690000
#define XPAR_PSV_FPD_SLCR_SECURE_0_S_AXI_HIGHADDR 0xFD69FFFF


/* Peripheral Definitions for peripheral PSV_FPD_SMMU_0 */
#define XPAR_PSV_FPD_SMMU_0_S_AXI_BASEADDR 0xFD5F0000
#define XPAR_PSV_FPD_SMMU_0_S_AXI_HIGHADDR 0xFD5FFFFF


/* Peripheral Definitions for peripheral PSV_FPD_SMMUTCU_0 */
#define XPAR_PSV_FPD_SMMUTCU_0_S_AXI_BASEADDR 0xFD800000
#define XPAR_PSV_FPD_SMMUTCU_0_S_AXI_HIGHADDR 0xFDFFFFFF


/* Peripheral Definitions for peripheral PSV_LPD_AFI_0 */
#define XPAR_PSV_LPD_AFI_0_S_AXI_BASEADDR 0xFF9B0000
#define XPAR_PSV_LPD_AFI_0_S_AXI_HIGHADDR 0xFF9BFFFF


/* Peripheral Definitions for peripheral PSV_LPD_IOU_SECURE_SLCR_0 */
#define XPAR_PSV_LPD_IOU_SECURE_SLCR_0_S_AXI_BASEADDR 0xFF0A0000
#define XPAR_PSV_LPD_IOU_SECURE_SLCR_0_S_AXI_HIGHADDR 0xFF0AFFFF


/* Peripheral Definitions for peripheral PSV_LPD_IOU_SLCR_0 */
#define XPAR_PSV_LPD_IOU_SLCR_0_S_AXI_BASEADDR 0xFF080000
#define XPAR_PSV_LPD_IOU_SLCR_0_S_AXI_HIGHADDR 0xFF09FFFF


/* Peripheral Definitions for peripheral PSV_LPD_SLCR_0 */
#define XPAR_PSV_LPD_SLCR_0_S_AXI_BASEADDR 0xFF410000
#define XPAR_PSV_LPD_SLCR_0_S_AXI_HIGHADDR 0xFF50FFFF


/* Peripheral Definitions for peripheral PSV_LPD_SLCR_SECURE_0 */
#define XPAR_PSV_LPD_SLCR_SECURE_0_S_AXI_BASEADDR 0xFF510000
#define XPAR_PSV_LPD_SLCR_SECURE_0_S_AXI_HIGHADDR 0xFF54FFFF


/* Peripheral Definitions for peripheral PSV_LPD_XPPU_0 */
#define XPAR_PSV_LPD_XPPU_0_S_AXI_BASEADDR 0xFF990000
#define XPAR_PSV_LPD_XPPU_0_S_AXI_HIGHADDR 0xFF99FFFF


/* Peripheral Definitions for peripheral PSV_OCM_CTRL */
#define XPAR_PSV_OCM_CTRL_S_AXI_BASEADDR 0xFF960000
#define XPAR_PSV_OCM_CTRL_S_AXI_HIGHADDR 0xFF96FFFF


/* Peripheral Definitions for peripheral PSV_OCM_RAM_0 */
#define XPAR_PSXL_OCM_RAM_0_S_AXI_BASEADDR 0xBBF00000
#define XPAR_PSXL_OCM_RAM_0_S_AXI_HIGHADDR 0xBBFFFFFF


/* Peripheral Definitions for peripheral PSV_OCM_XMPU_0 */
#define XPAR_PSV_OCM_XMPU_0_S_AXI_BASEADDR 0xFF980000
#define XPAR_PSV_OCM_XMPU_0_S_AXI_HIGHADDR 0xFF98FFFF


/* Peripheral Definitions for peripheral PSV_PMC_AES */
#define XPAR_PSV_PMC_AES_S_AXI_BASEADDR 0xF11E0000
#define XPAR_PSV_PMC_AES_S_AXI_HIGHADDR 0xF11EFFFF


/* Peripheral Definitions for peripheral PSV_PMC_BBRAM_CTRL */
#define XPAR_PSV_PMC_BBRAM_CTRL_S_AXI_BASEADDR 0xF11F0000
#define XPAR_PSV_PMC_BBRAM_CTRL_S_AXI_HIGHADDR 0xF11FFFFF


/* Peripheral Definitions for peripheral PSV_PMC_EFUSE_CTRL */
#define XPAR_PSV_PMC_EFUSE_CTRL_S_AXI_BASEADDR 0xF1240000
#define XPAR_PSV_PMC_EFUSE_CTRL_S_AXI_HIGHADDR 0xF124FFFF


/* Peripheral Definitions for peripheral PSV_PMC_GLOBAL_0 */
#define XPAR_PSV_PMC_GLOBAL_0_S_AXI_BASEADDR 0xF1110000
#define XPAR_PSV_PMC_GLOBAL_0_S_AXI_HIGHADDR 0xF115FFFF


/* Peripheral Definitions for peripheral PSV_PMC_QSPI_OSPI_FLASH_0 */
#define XPAR_PSV_PMC_QSPI_OSPI_FLASH_0_S_AXI_BASEADDR 0xC0000000
#define XPAR_PSV_PMC_QSPI_OSPI_FLASH_0_S_AXI_HIGHADDR 0xDFFFFFFF


/* Peripheral Definitions for peripheral PSV_PMC_RAM_DATA_CNTLR */
#define XPAR_PSV_PMC_RAM_DATA_CNTLR_S_AXI_BASEADDR 0xF0280000
#define XPAR_PSV_PMC_RAM_DATA_CNTLR_S_AXI_HIGHADDR 0xF028FFFF


/* Peripheral Definitions for peripheral PSV_PMC_RAM_INSTR_CNTLR */
#define XPAR_PSV_PMC_RAM_INSTR_CNTLR_S_AXI_BASEADDR 0xF0200000
#define XPAR_PSV_PMC_RAM_INSTR_CNTLR_S_AXI_HIGHADDR 0xF027FFFF


/* Peripheral Definitions for peripheral PSV_PMC_RSA */
#define XPAR_PSV_PMC_RSA_S_AXI_BASEADDR 0xF1200000
#define XPAR_PSV_PMC_RSA_S_AXI_HIGHADDR 0xF120FFFF


/* Peripheral Definitions for peripheral PSV_PMC_SHA */
#define XPAR_PSV_PMC_SHA_S_AXI_BASEADDR 0xF1210000
#define XPAR_PSV_PMC_SHA_S_AXI_HIGHADDR 0xF121FFFF


/* Peripheral Definitions for peripheral PSV_PMC_XMPU_0 */
#define XPAR_PSV_PMC_XMPU_0_S_AXI_BASEADDR 0xF12F0000
#define XPAR_PSV_PMC_XMPU_0_S_AXI_HIGHADDR 0xF12FFFFF


/* Peripheral Definitions for peripheral PSV_PMC_XPPU_0 */
#define XPAR_PSV_PMC_XPPU_0_S_AXI_BASEADDR 0xF1310000
#define XPAR_PSV_PMC_XPPU_0_S_AXI_HIGHADDR 0xF131FFFF


/* Peripheral Definitions for peripheral PSV_PMC_XPPU_NPI_0 */
#define XPAR_PSV_PMC_XPPU_NPI_0_S_AXI_BASEADDR 0xF1300000
#define XPAR_PSV_PMC_XPPU_NPI_0_S_AXI_HIGHADDR 0xF130FFFF


/* Peripheral Definitions for peripheral PSV_PSM_GLOBAL_REG */
#define XPAR_PSV_PSM_GLOBAL_REG_S_AXI_BASEADDR 0xEBC90000
#define XPAR_PSV_PSM_GLOBAL_REG_S_AXI_HIGHADDR 0xEBC9EFFF


/* Peripheral Definitions for peripheral PSV_R5_1_ATCM_GLOBAL */
#define XPAR_PSV_R5_1_ATCM_GLOBAL_S_AXI_BASEADDR 0xFFE90000
#define XPAR_PSV_R5_1_ATCM_GLOBAL_S_AXI_HIGHADDR 0xFFE9FFFF


/* Peripheral Definitions for peripheral PSV_R5_1_BTCM_GLOBAL */
#define XPAR_PSV_R5_1_BTCM_GLOBAL_S_AXI_BASEADDR 0xFFEB0000
#define XPAR_PSV_R5_1_BTCM_GLOBAL_S_AXI_HIGHADDR 0xFFEBFFFF


/* Peripheral Definitions for peripheral PSV_R5_TCM_RAM_GLOBAL */
#define XPAR_PSV_R5_TCM_RAM_GLOBAL_S_AXI_BASEADDR 0xFFE00000
#define XPAR_PSV_R5_TCM_RAM_GLOBAL_S_AXI_HIGHADDR 0xFFE3FFFF


/* Peripheral Definitions for peripheral PSV_SCNTR_0 */
#define XPAR_PSV_SCNTR_0_S_AXI_BASEADDR 0xFF130000
#define XPAR_PSV_SCNTR_0_S_AXI_HIGHADDR 0xFF13FFFF


/* Peripheral Definitions for peripheral PSV_SCNTRS_0 */
#define XPAR_PSV_SCNTRS_0_S_AXI_BASEADDR 0xFF140000
#define XPAR_PSV_SCNTRS_0_S_AXI_HIGHADDR 0xFF14FFFF


/* Peripheral Definitions for peripheral PSV_USB_0 */
#define XPAR_PSV_USB_0_S_AXI_BASEADDR 0xF1E00000
#define XPAR_PSV_USB_0_S_AXI_HIGHADDR 0xF1E0FFFF


/******************************************************************/
/* Definitions for driver WDTTB */
#define XPAR_XWDTTB_NUM_INSTANCES 1U

/* Canonical definitions for peripheral PSX_PMX_WWDT_0 */
#define XPAR_WDTTB_0_DEVICE_ID 0U
#define XPAR_WDTTB_0_BASEADDR 0xF03F0000U
#define XPAR_WDTTB_0_HIGHADDR 0xF03FFFFFU
#define XPAR_WDTTB_0_ENABLE_WINDOW_WDT 0U
#define XPAR_WDTTB_0_MAX_COUNT_WIDTH 0U
#define XPAR_WDTTB_0_SST_COUNT_WIDTH 0U
#define XPAR_WDTTB_0_IS_PL 0U
#define XPAR_WDTTB_0_WDT_CLK_FREQ_HZ 100000000U

/* Canonical Definitions for peripheral PSV_CORESIGHT_FPD_STM */
#define XPAR_PSV_CORESIGHT_FPD_STM_0_S_AXI_BASEADDR 0xF0B70000
#define XPAR_PSV_CORESIGHT_FPD_STM_0_S_AXI_HIGHADDR 0xF0B7FFFF










/* Canonical Definitions for peripheral PSV_FPD_AFI_2 */
#define XPAR_PSV_FPD_AFI_1_S_AXI_BASEADDR 0xFD380000
#define XPAR_PSV_FPD_AFI_1_S_AXI_HIGHADDR 0xFD38FFFF






/* Canonical Definitions for peripheral PSV_FPD_MAINCCI_0 */
#define XPAR_PSV_FPD_MAINCCI_0_0_S_AXI_BASEADDR 0xFD000000
#define XPAR_PSV_FPD_MAINCCI_0_0_S_AXI_HIGHADDR 0xFD0FFFFF










/* Canonical Definitions for peripheral PSV_FPD_SMMUTCU_0 */
#define XPAR_PSV_FPD_SMMUTCU_1_S_AXI_BASEADDR 0xFD800000
#define XPAR_PSV_FPD_SMMUTCU_1_S_AXI_HIGHADDR 0xFDFFFFFF














/* Canonical Definitions for peripheral PSV_OCM_CTRL */
#define XPAR_PSV_OCM_0_S_AXI_BASEADDR 0xFF960000
#define XPAR_PSV_OCM_0_S_AXI_HIGHADDR 0xFF96FFFF






/* Canonical Definitions for peripheral PSV_PMC_AES */
#define XPAR_PSV_PMC_AES_0_S_AXI_BASEADDR 0xF11E0000
#define XPAR_PSV_PMC_AES_0_S_AXI_HIGHADDR 0xF11EFFFF


/* Canonical Definitions for peripheral PSV_PMC_BBRAM_CTRL */
#define XPAR_PSV_PMC_BBRAM_CTRL_0_S_AXI_BASEADDR 0xF11F0000
#define XPAR_PSV_PMC_BBRAM_CTRL_0_S_AXI_HIGHADDR 0xF11FFFFF


/* Canonical Definitions for peripheral PSV_PMC_EFUSE_CTRL */
#define XPAR_PSV_PMC_EFUSE_CTRL_0_S_AXI_BASEADDR 0xF1240000
#define XPAR_PSV_PMC_EFUSE_CTRL_0_S_AXI_HIGHADDR 0xF124FFFF




/* Canonical Definitions for peripheral PSV_PMC_QSPI_OSPI_FLASH_0 */
#define XPAR_PSV_PMC_QSPI_OSPI_0_S_AXI_BASEADDR 0xC0000000
#define XPAR_PSV_PMC_QSPI_OSPI_0_S_AXI_HIGHADDR 0xDFFFFFFF


/* Canonical Definitions for peripheral PSV_PMC_RAM_DATA_CNTLR */
#define XPAR_RAM_DATA_CNTLR_0_S_AXI_BASEADDR 0xF0240000
#define XPAR_RAM_DATA_CNTLR_0_S_AXI_HIGHADDR 0xF025FFFF


/* Canonical Definitions for peripheral PSV_PMC_RAM_INSTR_CNTLR */
#define XPAR_RAM_INSTR_CNTLR_0_S_AXI_BASEADDR 0xF0200000
#define XPAR_RAM_INSTR_CNTLR_0_S_AXI_HIGHADDR 0xF023FFFF


/* Canonical Definitions for peripheral PSV_PMC_RSA */
#define XPAR_PSV_PMC_RSA_0_S_AXI_BASEADDR 0xF1200000
#define XPAR_PSV_PMC_RSA_0_S_AXI_HIGHADDR 0xF120FFFF


/* Canonical Definitions for peripheral PSV_PMC_SHA */
#define XPAR_PSV_PMC_SHA_0_S_AXI_BASEADDR 0xF1210000
#define XPAR_PSV_PMC_SHA_0_S_AXI_HIGHADDR 0xF121FFFF








/* Canonical Definitions for peripheral PSV_PSM_GLOBAL_REG */
#define XPAR_PSV_PSM_GLOBAL_REG_0_S_AXI_BASEADDR 0xFFC90000
#define XPAR_PSV_PSM_GLOBAL_REG_0_S_AXI_HIGHADDR 0xFFC9EFFF


/* Canonical Definitions for peripheral PSV_R5_1_ATCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_0_S_AXI_BASEADDR 0xFFE90000
#define XPAR_PSV_TCM_GLOBAL_0_S_AXI_HIGHADDR 0xFFE9FFFF


/* Canonical Definitions for peripheral PSV_R5_1_BTCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_1_S_AXI_BASEADDR 0xFFEB0000
#define XPAR_PSV_TCM_GLOBAL_1_S_AXI_HIGHADDR 0xFFEBFFFF


/* Canonical Definitions for peripheral PSV_R5_TCM_RAM_GLOBAL */
#define XPAR_PSV_R5_TCM_0_S_AXI_BASEADDR 0xFFE00000
#define XPAR_PSV_R5_TCM_0_S_AXI_HIGHADDR 0xFFE3FFFF








/******************************************************************/

/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_GPIO_0 */
#define XPAR_PSV_PMC_GPIO_0_DEVICE_ID 0
#define XPAR_PSV_PMC_GPIO_0_BASEADDR 0xF1020000
#define XPAR_PSV_PMC_GPIO_0_HIGHADDR 0xF102FFFF


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSV_PMC_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xF1020000
#define XPAR_XGPIOPS_0_HIGHADDR 0xF102FFFF


/******************************************************************/

/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 2

/* Definitions for peripheral PSV_I2C_1 */
#define XPAR_PSV_I2C_1_DEVICE_ID 0
#define XPAR_PSV_I2C_1_BASEADDR 0xFF030000
#define XPAR_PSV_I2C_1_HIGHADDR 0xFF03FFFF
#define XPAR_PSV_I2C_1_I2C_CLK_FREQ_HZ 99999992


/* Definitions for peripheral PSV_PMC_I2C_0 */
#define XPAR_PSV_PMC_I2C_0_DEVICE_ID 1
#define XPAR_PSV_PMC_I2C_0_BASEADDR 0xF1000000
#define XPAR_PSV_PMC_I2C_0_HIGHADDR 0xF100FFFF
#define XPAR_PSV_PMC_I2C_0_I2C_CLK_FREQ_HZ 99999992


/******************************************************************/

/* Canonical definitions for peripheral PSV_I2C_1 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSV_I2C_1_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xFF030000
#define XPAR_XIICPS_0_HIGHADDR 0xFF03FFFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99999992

/* Canonical definitions for peripheral PSV_PMC_I2C_0 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PSV_PMC_I2C_0_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xF1000000
#define XPAR_XIICPS_1_HIGHADDR 0xF100FFFF
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99999992


/******************************************************************/

/* Definition for input Clock */
/* Definition for input Clock */
/* Definitions for driver IOMODULE */
#define XPAR_XIOMODULE_NUM_INSTANCES 1U

/* Definitions for peripheral PSV_PMC_IOMODULE_0 */
#define XPAR_PSV_PMC_IOMODULE_0_DEVICE_ID 0U
#define XPAR_PSV_PMC_IOMODULE_0_BASEADDR 0xF0300000U
#define XPAR_PSV_PMC_IOMODULE_0_HIGHADDR 0xF0300FFFU
#define XPAR_PSV_PMC_IOMODULE_0_MASK 0x00000000FFFFF000U
#define XPAR_PSV_PMC_IOMODULE_0_FREQ 100000000U
#define XPAR_PSV_PMC_IOMODULE_0_USE_UART_RX 1U
#define XPAR_PSV_PMC_IOMODULE_0_USE_UART_TX 1U
#define XPAR_PSV_PMC_IOMODULE_0_UART_BAUDRATE 115200U
#define XPAR_PSV_PMC_IOMODULE_0_UART_PROG_BAUDRATE 1U
#define XPAR_PSV_PMC_IOMODULE_0_UART_DATA_BITS 8U
#define XPAR_PSV_PMC_IOMODULE_0_UART_USE_PARITY 0U
#define XPAR_PSV_PMC_IOMODULE_0_UART_ODD_PARITY 0U
#define XPAR_PSV_PMC_IOMODULE_0_UART_RX_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_UART_TX_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_UART_ERROR_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_USE_FIT1 0U
#define XPAR_PSV_PMC_IOMODULE_0_FIT1_NO_CLOCKS 6216U
#define XPAR_PSV_PMC_IOMODULE_0_FIT1_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_FIT2 0U
#define XPAR_PSV_PMC_IOMODULE_0_FIT2_NO_CLOCKS 6216U
#define XPAR_PSV_PMC_IOMODULE_0_FIT2_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_FIT3 0U
#define XPAR_PSV_PMC_IOMODULE_0_FIT3_NO_CLOCKS 6216U
#define XPAR_PSV_PMC_IOMODULE_0_FIT3_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_FIT4 0U
#define XPAR_PSV_PMC_IOMODULE_0_FIT4_NO_CLOCKS 6216U
#define XPAR_PSV_PMC_IOMODULE_0_FIT4_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_PIT1 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT1_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_PIT1_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_PSV_PMC_IOMODULE_0_PIT1_READABLE 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT1_PRESCALER 9U
#define XPAR_PSV_PMC_IOMODULE_0_PIT1_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_USE_PIT2 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT2_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_PIT2_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_PSV_PMC_IOMODULE_0_PIT2_READABLE 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT2_PRESCALER 0U
#define XPAR_PSV_PMC_IOMODULE_0_PIT2_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_USE_PIT3 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT3_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_PIT3_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_PSV_PMC_IOMODULE_0_PIT3_READABLE 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT3_PRESCALER 9U
#define XPAR_PSV_PMC_IOMODULE_0_PIT3_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_USE_PIT4 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT4_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_PIT4_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_PSV_PMC_IOMODULE_0_PIT4_READABLE 1U
#define XPAR_PSV_PMC_IOMODULE_0_PIT4_PRESCALER 0U
#define XPAR_PSV_PMC_IOMODULE_0_PIT4_INTERRUPT 1U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPO1 1U
#define XPAR_PSV_PMC_IOMODULE_0_GPO1_SIZE 3U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPO2 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPO2_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPO3 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPO3_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPO4 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPO4_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPI1 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPI1_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_GPI1_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPI2 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPI2_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_GPI2_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPI3 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPI3_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_GPI3_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_GPI4 0U
#define XPAR_PSV_PMC_IOMODULE_0_GPI4_SIZE 32U
#define XPAR_PSV_PMC_IOMODULE_0_GPI4_INTERRUPT 0U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_USE_EXT_INTR 1U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_INTR_SIZE 16U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_HAS_FAST 0U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_BASE_VECTORS 0xF0240000U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_ADDR_WIDTH 32U
#define XPAR_PSV_PMC_IOMODULE_0_ 0U
#define XPAR_PSV_PMC_IOMODULE_0_USE_IO_BUS 0U
#define XPAR_PSV_PMC_IOMODULE_0_IO_BASEADDR 0xFFFFFFFFFFFFFFFFU
#define XPAR_PSV_PMC_IOMODULE_0_IO_HIGHADDR 0x00000000U
#define XPAR_PSV_PMC_IOMODULE_0_IO_MASK 0x00000000FFFE0000U


/******************************************************************/


/* Additional definitions for peripheral PSV_PMC_IOMODULE_0 */
#define XPAR_PSV_PMC_IOMODULE_0_GPO1_INIT 0x00000000U
#define XPAR_PSV_PMC_IOMODULE_0_GPO2_INIT 0x00000000U
#define XPAR_PSV_PMC_IOMODULE_0_GPO3_INIT 0x00000000U
#define XPAR_PSV_PMC_IOMODULE_0_GPO4_INIT 0x00000000U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_LEVEL_EDGE 0x0000U
#define XPAR_PSV_PMC_IOMODULE_0_INTC_POSITIVE 0xFFFFU


/******************************************************************/

#define XPAR_IOMODULE_SINGLE_BASEADDR 0xF0280000
#define XPAR_IOMODULE_SINGLE_HIGHADDR 0xF0280FFF
#define XPAR_IOMODULE_INTC_SINGLE_DEVICE_ID XPAR_PSV_PMC_IOMODULE_0_DEVICE_ID
#define XPAR_IOMODULE_INTC_MAX_INTR_SIZE 32U

/******************************************************************/


/* Canonical definitions for peripheral PSV_PMC_IOMODULE_0 */
#define XPAR_IOMODULE_0_NUM_INSTANCES 0U
#define XPAR_IOMODULE_0_DEVICE_ID 0U
#define XPAR_IOMODULE_0_BASEADDR 0xF0300000U
#define XPAR_IOMODULE_0_HIGHADDR 0xF0300FFFU
#define XPAR_IOMODULE_0_MASK 0x00000000FFFFF000U
#define XPAR_IOMODULE_0_FREQ 100000000U
#define XPAR_IOMODULE_0_USE_UART_RX 1U
#define XPAR_IOMODULE_0_USE_UART_TX 1U
#define XPAR_IOMODULE_0_UART_BAUDRATE 115200U
#define XPAR_IOMODULE_0_UART_PROG_BAUDRATE 1U
#define XPAR_IOMODULE_0_UART_DATA_BITS 8U
#define XPAR_IOMODULE_0_UART_USE_PARITY 0U
#define XPAR_IOMODULE_0_UART_ODD_PARITY 0U
#define XPAR_IOMODULE_0_UART_RX_INTERRUPT 1U
#define XPAR_IOMODULE_0_UART_TX_INTERRUPT 1U
#define XPAR_IOMODULE_0_UART_ERROR_INTERRUPT 1U
#define XPAR_IOMODULE_0_USE_FIT1 0U
#define XPAR_IOMODULE_0_FIT1_NO_CLOCKS 6216U
#define XPAR_IOMODULE_0_FIT1_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_FIT2 0U
#define XPAR_IOMODULE_0_FIT2_NO_CLOCKS 6216U
#define XPAR_IOMODULE_0_FIT2_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_FIT3 0U
#define XPAR_IOMODULE_0_FIT3_NO_CLOCKS 6216U
#define XPAR_IOMODULE_0_FIT3_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_FIT4 0U
#define XPAR_IOMODULE_0_FIT4_NO_CLOCKS 6216U
#define XPAR_IOMODULE_0_FIT4_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_PIT1 1U
#define XPAR_IOMODULE_0_PIT1_SIZE 32U
#define XPAR_IOMODULE_0_PIT1_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_IOMODULE_0_PIT1_READABLE 1U
#define XPAR_IOMODULE_0_PIT1_PRESCALER 9U
#define XPAR_IOMODULE_0_PIT1_INTERRUPT 1U
#define XPAR_IOMODULE_0_USE_PIT2 1U
#define XPAR_IOMODULE_0_PIT2_SIZE 32U
#define XPAR_IOMODULE_0_PIT2_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_IOMODULE_0_PIT2_READABLE 1U
#define XPAR_IOMODULE_0_PIT2_PRESCALER 0U
#define XPAR_IOMODULE_0_PIT2_INTERRUPT 1U
#define XPAR_IOMODULE_0_USE_PIT3 1U
#define XPAR_IOMODULE_0_PIT3_SIZE 32U
#define XPAR_IOMODULE_0_PIT3_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_IOMODULE_0_PIT3_READABLE 1U
#define XPAR_IOMODULE_0_PIT3_PRESCALER 9U
#define XPAR_IOMODULE_0_PIT3_INTERRUPT 1U
#define XPAR_IOMODULE_0_USE_PIT4 1U
#define XPAR_IOMODULE_0_PIT4_SIZE 32U
#define XPAR_IOMODULE_0_PIT4_EXPIRED_MASK 0xFFFFFFFFU
#define XPAR_IOMODULE_0_PIT4_READABLE 1U
#define XPAR_IOMODULE_0_PIT4_PRESCALER 0U
#define XPAR_IOMODULE_0_PIT4_INTERRUPT 1U
#define XPAR_IOMODULE_0_USE_GPO1 1U
#define XPAR_IOMODULE_0_GPO1_SIZE 3U
#define XPAR_IOMODULE_0_USE_GPO2 0U
#define XPAR_IOMODULE_0_GPO2_SIZE 32U
#define XPAR_IOMODULE_0_USE_GPO3 0U
#define XPAR_IOMODULE_0_GPO3_SIZE 32U
#define XPAR_IOMODULE_0_USE_GPO4 0U
#define XPAR_IOMODULE_0_GPO4_SIZE 32U
#define XPAR_IOMODULE_0_USE_GPI1 0U
#define XPAR_IOMODULE_0_GPI1_SIZE 32U
#define XPAR_IOMODULE_0_GPI1_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_GPI2 0U
#define XPAR_IOMODULE_0_GPI2_SIZE 32U
#define XPAR_IOMODULE_0_GPI2_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_GPI3 0U
#define XPAR_IOMODULE_0_GPI3_SIZE 32U
#define XPAR_IOMODULE_0_GPI3_INTERRUPT 0U
#define XPAR_IOMODULE_0_USE_GPI4 0U
#define XPAR_IOMODULE_0_GPI4_SIZE 32U
#define XPAR_IOMODULE_0_GPI4_INTERRUPT 0U
#define XPAR_IOMODULE_0_INTC_USE_EXT_INTR 1U
#define XPAR_IOMODULE_0_INTC_INTR_SIZE 16U
#define XPAR_IOMODULE_0_INTC_HAS_FAST 0U
#define XPAR_IOMODULE_0_INTC_BASE_VECTORS 0xF0240000U
#define XPAR_IOMODULE_0_INTC_ADDR_WIDTH 32U
#define XPAR_IOMODULE_0_ 0U
#define XPAR_IOMODULE_0_USE_IO_BUS 0U
#define XPAR_IOMODULE_0_IO_BASEADDR 0xFFFFFFFFFFFFFFFFU
#define XPAR_IOMODULE_0_IO_HIGHADDR 0x00000000U
#define XPAR_IOMODULE_0_IO_MASK 0x00000000FFFE0000U
#define XPAR_IOMODULE_0_GPO1_INIT 0x00000000U
#define XPAR_IOMODULE_0_GPO2_INIT 0x00000000U
#define XPAR_IOMODULE_0_GPO3_INIT 0x00000000U
#define XPAR_IOMODULE_0_GPO4_INIT 0x00000000U
#define XPAR_IOMODULE_0_INTC_LEVEL_EDGE 0x0000U
#define XPAR_IOMODULE_0_INTC_POSITIVE 0xFFFFU


/******************************************************************/

#define  XPAR_XIPIPSU_NUM_INSTANCES  2U

/* Parameter definitions for peripheral psv_ipi_pmc */
#define  XPAR_PSV_IPI_PMC_DEVICE_ID  0U
#define  XPAR_PSV_IPI_PMC_S_AXI_BASEADDR  0xEB320000U
#define  XPAR_PSV_IPI_PMC_BIT_MASK  0x00000002U
#define  XPAR_PSV_IPI_PMC_BUFFER_INDEX  0x1U
#define  XPAR_PSV_IPI_PMC_INT_ID  59U

/* Parameter definitions for peripheral psv_ipi_pmc_nobuf */
#define  XPAR_PSV_IPI_PMC_NOBUF_DEVICE_ID  1U
#define  XPAR_PSV_IPI_PMC_NOBUF_S_AXI_BASEADDR  0xEB390000U
#define  XPAR_PSV_IPI_PMC_NOBUF_BIT_MASK  0x00000100U
#define  XPAR_PSV_IPI_PMC_NOBUF_BUFFER_INDEX  0xFFFFU
#define  XPAR_PSV_IPI_PMC_NOBUF_INT_ID  60U

/* Canonical definitions for peripheral psv_ipi_pmc */
#define  XPAR_XIPIPSU_0_DEVICE_ID	XPAR_PSV_IPI_PMC_DEVICE_ID
#define  XPAR_XIPIPSU_0_BASE_ADDRESS	XPAR_PSV_IPI_PMC_S_AXI_BASEADDR
#define  XPAR_XIPIPSU_0_BIT_MASK	XPAR_PSV_IPI_PMC_BIT_MASK
#define  XPAR_XIPIPSU_0_BUFFER_INDEX	XPAR_PSV_IPI_PMC_BUFFER_INDEX
#define  XPAR_XIPIPSU_0_INT_ID	XPAR_PSV_IPI_PMC_INT_ID

/* Canonical definitions for peripheral psv_ipi_pmc_nobuf */
#define  XPAR_XIPIPSU_1_DEVICE_ID	XPAR_PSV_IPI_PMC_NOBUF_DEVICE_ID
#define  XPAR_XIPIPSU_1_BASE_ADDRESS	XPAR_PSV_IPI_PMC_NOBUF_S_AXI_BASEADDR
#define  XPAR_XIPIPSU_1_BIT_MASK	XPAR_PSV_IPI_PMC_NOBUF_BIT_MASK
#define  XPAR_XIPIPSU_1_BUFFER_INDEX	XPAR_PSV_IPI_PMC_NOBUF_BUFFER_INDEX
#define  XPAR_XIPIPSU_1_INT_ID	XPAR_PSV_IPI_PMC_NOBUF_INT_ID

#define  XPAR_XIPIPSU_NUM_TARGETS  10U

#define  XPAR_PSV_IPI_0_BIT_MASK  0x00000004U
#define  XPAR_PSV_IPI_0_BUFFER_INDEX  0x2U
#define  XPAR_PSV_IPI_1_BIT_MASK  0x00000008U
#define  XPAR_PSV_IPI_1_BUFFER_INDEX  0x3U
#define  XPAR_PSV_IPI_2_BIT_MASK  0x00000010U
#define  XPAR_PSV_IPI_2_BUFFER_INDEX  0x4U
#define  XPAR_PSV_IPI_3_BIT_MASK  0x00000020U
#define  XPAR_PSV_IPI_3_BUFFER_INDEX  0x5U
#define  XPAR_PSV_IPI_4_BIT_MASK  0x00000040U
#define  XPAR_PSV_IPI_4_BUFFER_INDEX  0x6U
#define  XPAR_PSV_IPI_5_BIT_MASK  0x00000080U
#define  XPAR_PSV_IPI_5_BUFFER_INDEX  0x7U
#define  XPAR_PSV_IPI_6_BIT_MASK  0x00000200U
#define  XPAR_PSV_IPI_6_BUFFER_INDEX  0xFFFFU
#define  XPAR_PSV_IPI_PMC_BIT_MASK  0x00000002U
#define  XPAR_PSV_IPI_PMC_BUFFER_INDEX  0x1U
#define  XPAR_PSV_IPI_PMC_NOBUF_BIT_MASK  0x00000100U
#define  XPAR_PSV_IPI_PMC_NOBUF_BUFFER_INDEX  0xFFFFU
#define  XPAR_PSV_IPI_PSM_BIT_MASK  0x00000001U
#define  XPAR_PSV_IPI_PSM_BUFFER_INDEX  0x0U
/* Target List for referring to processor IPI Targets */

#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH0_MASK  XPAR_PSV_IPI_0_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH0_INDEX  0U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH1_MASK  XPAR_PSV_IPI_1_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH1_INDEX  1U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH2_MASK  XPAR_PSV_IPI_2_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH2_INDEX  2U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH3_MASK  XPAR_PSV_IPI_3_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH3_INDEX  3U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH4_MASK  XPAR_PSV_IPI_4_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH4_INDEX  4U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH5_MASK  XPAR_PSV_IPI_5_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH5_INDEX  5U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH6_MASK  XPAR_PSV_IPI_6_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_0_CH6_INDEX  6U

#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH0_MASK  XPAR_PSV_IPI_0_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH0_INDEX  0U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH1_MASK  XPAR_PSV_IPI_1_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH1_INDEX  1U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH2_MASK  XPAR_PSV_IPI_2_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH2_INDEX  2U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH3_MASK  XPAR_PSV_IPI_3_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH3_INDEX  3U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH4_MASK  XPAR_PSV_IPI_4_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH4_INDEX  4U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH5_MASK  XPAR_PSV_IPI_5_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH5_INDEX  5U
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH6_MASK  XPAR_PSV_IPI_6_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_CORTEXA72_1_CH6_INDEX  6U



#define  XPAR_XIPIPS_TARGET_PSV_PMC_0_CH0_MASK  XPAR_PSV_IPI_PMC_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_PMC_0_CH0_INDEX  7U
#define  XPAR_XIPIPS_TARGET_PSV_PMC_0_CH1_MASK  XPAR_PSV_IPI_PMC_NOBUF_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSV_PMC_0_CH1_INDEX  8U

#define  XPAR_XIPIPS_TARGET_PSXL_PSM_0_CH0_MASK  XPAR_PSV_IPI_PSM_BIT_MASK
#define  XPAR_XIPIPS_TARGET_PSXL_PSM_0_CH0_INDEX  9U

/* Definitions for driver PMONPSV */
#define XPAR_XPMONPSV_NUM_INSTANCES 2

/* Definitions for peripheral PSV_CORESIGHT_FPD_ATM */
#define XPAR_PSV_CORESIGHT_FPD_ATM_DEVICE_ID 0
#define XPAR_PSV_CORESIGHT_FPD_ATM_S_AXI_BASEADDR 0xF0B80000


/* Definitions for peripheral PSV_CORESIGHT_LPD_ATM */
#define XPAR_PSV_CORESIGHT_LPD_ATM_DEVICE_ID 1
#define XPAR_PSV_CORESIGHT_LPD_ATM_S_AXI_BASEADDR 0xF0980000


/******************************************************************/

/* Canonical definitions for peripheral PSV_CORESIGHT_FPD_ATM */
#define XPAR_XPMONPSV_0_DEVICE_ID XPAR_PSV_CORESIGHT_FPD_ATM_DEVICE_ID
#define XPAR_XPMONPSV_0_S_AXI_BASEADDR 0xF0B80000

/* Canonical definitions for peripheral PSV_CORESIGHT_LPD_ATM */
#define XPAR_XPMONPSV_1_DEVICE_ID XPAR_PSV_CORESIGHT_LPD_ATM_DEVICE_ID
#define XPAR_XPMONPSV_1_S_AXI_BASEADDR 0xF0980000


/******************************************************************/

/* Definitions for driver QSPIPSU */
#define XPAR_XQSPIPSU_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_QSPI_0 */
#define XPAR_PSV_PMC_QSPI_0_DEVICE_ID 0
#define XPAR_PSV_PMC_QSPI_0_BASEADDR 0xF1030000
#define XPAR_PSV_PMC_QSPI_0_HIGHADDR 0xF103FFFF
#define XPAR_PSV_PMC_QSPI_0_QSPI_CLK_FREQ_HZ 295833313
#define XPAR_PSV_PMC_QSPI_0_QSPI_MODE 2
#define XPAR_PSV_PMC_QSPI_0_QSPI_BUS_WIDTH 2


/******************************************************************/

#define XPAR_PSV_PMC_QSPI_0_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PSV_PMC_QSPI_0 */
#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSV_PMC_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPSU_0_BASEADDR 0xF1030000
#define XPAR_XQSPIPSU_0_HIGHADDR 0xF103FFFF
#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 295833313
#define XPAR_XQSPIPSU_0_QSPI_MODE 2
#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2
#define XPAR_XQSPIPSU_0_IS_CACHE_COHERENT 0

/* Definitions for driver OSPIPSV */
#define XPAR_XOSPIPSV_NUM_INSTANCES 1

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_OSPI_0 */
#define XPAR_PSV_PMC_OSPI_0_DEVICE_ID 0
#define XPAR_PSV_PMC_OSPI_0_BASEADDR 0xF1010000
#define XPAR_PSV_PMC_OSPI_0_HIGHADDR 0xF101FFFF
#define XPAR_PSV_PMC_OSPI_0_OSPI_CLK_FREQ_HZ 133332000
#define XPAR_PSV_PMC_OSPI_0_IS_CACHE_COHERENT 0
#define XPAR_PSV_PMC_OSPI_0_OSPI_MODE 0


/******************************************************************/

#define XPAR_PSV_PMC_OSPI_0_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_OSPI_0 */
#define XPAR_XOSPIPSV_0_DEVICE_ID XPAR_PSV_PMC_OSPI_0_DEVICE_ID
#define XPAR_XOSPIPSV_0_BASEADDR 0xF1010000
#define XPAR_XOSPIPSV_0_HIGHADDR 0xF101FFFF
#define XPAR_XOSPIPSV_0_OSPI_CLK_FREQ_HZ 133332000
#define XPAR_XOSPIPSV_0_IS_CACHE_COHERENT 0
#define XPAR_XOSPIPSV_0_OSPI_MODE 0

/******************************************************************/

/* Definitions for driver RTCPSU */
#define XPAR_XRTCPSU_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_RTC_0 */
#define XPAR_PSV_PMC_RTC_0_DEVICE_ID 0
#define XPAR_PSV_PMC_RTC_0_BASEADDR 0xF12A0000
#define XPAR_PSV_PMC_RTC_0_HIGHADDR 0xF12AFFFF


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_RTC_0 */
#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSV_PMC_RTC_0_DEVICE_ID
#define XPAR_XRTCPSU_0_BASEADDR 0xF12A0000
#define XPAR_XRTCPSU_0_HIGHADDR 0xF12AFFFF


/******************************************************************/

/* Definitions for driver SDPS */
#define XPAR_XSDPS_NUM_INSTANCES 2

/* Definitions for peripheral PSV_PMC_SD_0 */
#define XPAR_PSV_PMC_SD_0_DEVICE_ID 0
#define XPAR_PSV_PMC_SD_0_BASEADDR 0xF1040000
#define XPAR_PSV_PMC_SD_0_HIGHADDR 0xF104FFFF
#define XPAR_PSV_PMC_SD_0_SDIO_CLK_FREQ_HZ 199998001
#define XPAR_PSV_PMC_SD_0_HAS_CD 1
#define XPAR_PSV_PMC_SD_0_HAS_WP 0
#define XPAR_PSV_PMC_SD_0_BUS_WIDTH 8
#define XPAR_PSV_PMC_SD_0_MIO_BANK 0
#define XPAR_PSV_PMC_SD_0_HAS_EMIO 0
#define XPAR_PSV_PMC_SD_0_SLOT_TYPE 0
#define XPAR_PSV_PMC_SD_0_CLK_50_SDR_ITAP_DLY 0
#define XPAR_PSV_PMC_SD_0_CLK_50_SDR_OTAP_DLY 0
#define XPAR_PSV_PMC_SD_0_CLK_50_DDR_ITAP_DLY 0
#define XPAR_PSV_PMC_SD_0_CLK_50_DDR_OTAP_DLY 0
#define XPAR_PSV_PMC_SD_0_CLK_100_SDR_OTAP_DLY 0
#define XPAR_PSV_PMC_SD_0_CLK_200_SDR_OTAP_DLY 0


/* Definitions for peripheral PSV_PMC_SD_1 */
#define XPAR_PSV_PMC_SD_1_DEVICE_ID 1
#define XPAR_PSV_PMC_SD_1_BASEADDR 0xF1050000
#define XPAR_PSV_PMC_SD_1_HIGHADDR 0xF105FFFF
#define XPAR_PSV_PMC_SD_1_SDIO_CLK_FREQ_HZ 199998001
#define XPAR_PSV_PMC_SD_1_HAS_CD 0
#define XPAR_PSV_PMC_SD_1_HAS_WP 0
#define XPAR_PSV_PMC_SD_1_BUS_WIDTH 8
#define XPAR_PSV_PMC_SD_1_MIO_BANK 1
#define XPAR_PSV_PMC_SD_1_HAS_EMIO 0
#define XPAR_PSV_PMC_SD_1_SLOT_TYPE 0
#define XPAR_PSV_PMC_SD_1_CLK_50_SDR_ITAP_DLY 0
#define XPAR_PSV_PMC_SD_1_CLK_50_SDR_OTAP_DLY 0
#define XPAR_PSV_PMC_SD_1_CLK_50_DDR_ITAP_DLY 0
#define XPAR_PSV_PMC_SD_1_CLK_50_DDR_OTAP_DLY 0
#define XPAR_PSV_PMC_SD_1_CLK_100_SDR_OTAP_DLY 0
#define XPAR_PSV_PMC_SD_1_CLK_200_SDR_OTAP_DLY 0


/******************************************************************/

#define XPAR_PSV_PMC_SD_0_IS_CACHE_COHERENT 0
#define XPAR_PSV_PMC_SD_1_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PSV_PMC_SD_0 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSV_PMC_SD_0_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xF1040000
#define XPAR_XSDPS_0_HIGHADDR 0xF104FFFF
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998001
#define XPAR_XSDPS_0_HAS_CD 1
#define XPAR_XSDPS_0_HAS_WP 0
#define XPAR_XSDPS_0_BUS_WIDTH 8
#define XPAR_XSDPS_0_MIO_BANK 0
#define XPAR_XSDPS_0_HAS_EMIO 0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0

/* Canonical definitions for peripheral PSV_PMC_SD_1 */
#define XPAR_XSDPS_1_DEVICE_ID XPAR_PSV_PMC_SD_1_DEVICE_ID
#define XPAR_XSDPS_1_BASEADDR 0xF1050000
#define XPAR_XSDPS_1_HIGHADDR 0xF105FFFF
#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 199998001
#define XPAR_XSDPS_1_HAS_CD 0
#define XPAR_XSDPS_1_HAS_WP 0
#define XPAR_XSDPS_1_BUS_WIDTH 8
#define XPAR_XSDPS_1_MIO_BANK 1
#define XPAR_XSDPS_1_HAS_EMIO 0
#define XPAR_XSDPS_1_IS_CACHE_COHERENT 0


/******************************************************************/

#define XPAR_XSYSMONPSV_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_SYSMON_0 */
#define XPAR_PSV_PMC_SYSMON_0_S_AXI_BASEADDR 0xF1270000
#define XPAR_PSV_PMC_SYSMON_0_S_AXI_HIGHADDR 0xF129FFFF


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_SYSMON_0 */
#define XPAR_XSYSMONPSV_0_S_AXI_BASEADDR 0xF1270000
#define XPAR_XSYSMONPSV_0_S_AXI_HIGHADDR 0xF129FFFF

#define XPAR_XSYSMONPSV_0_NO_MEAS	161

/******************************************************************/

/* Xilinx Sysmon Device Name */

/******************************************************************/

/* Definitions for driver TMR_INJECT */
#define XPAR_XTMR_INJECT_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_TMR_INJECT_0 */
#define XPAR_PSV_PMC_TMR_INJECT_0_DEVICE_ID 0
#define XPAR_PSV_PMC_TMR_INJECT_0_BASEADDR 0xF0284000
#define XPAR_PSV_PMC_TMR_INJECT_0_HIGHADDR 0xF0284FFF
#define XPAR_PSV_PMC_TMR_INJECT_0_MASK 0x0000000000084000
#define XPAR_PSV_PMC_TMR_INJECT_0_MAGIC 0x27
#define XPAR_PSV_PMC_TMR_INJECT_0_CPU_ID 1
#define XPAR_PSV_PMC_TMR_INJECT_0_INJECT_LMB_AWIDTH 0


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_TMR_INJECT_0 */
#define XPAR_TMR_INJECT_0_DEVICE_ID XPAR_PSV_PMC_TMR_INJECT_0_DEVICE_ID
#define XPAR_TMR_INJECT_0_BASEADDR 0xF0284000
#define XPAR_TMR_INJECT_0_HIGHADDR 0xF0284FFF
#define XPAR_TMR_INJECT_0_MASK 0x0000000000084000
#define XPAR_TMR_INJECT_0_MAGIC 0x27
#define XPAR_TMR_INJECT_0_CPU_ID 1
#define XPAR_TMR_INJECT_0_INJECT_LMB_AWIDTH 0


/******************************************************************/

/* Definitions for driver TMR_MANAGER */
#define XPAR_XTMR_MANAGER_NUM_INSTANCES 1

/* Definitions for peripheral PSV_PMC_TMR_MANAGER_0 */
#define XPAR_PSV_PMC_TMR_MANAGER_0_DEVICE_ID 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_BASEADDR 0xF0283000
#define XPAR_PSV_PMC_TMR_MANAGER_0_HIGHADDR 0xF0283FFF
#define XPAR_PSV_PMC_TMR_MANAGER_0_MASK 0x0000000000083000
#define XPAR_PSV_PMC_TMR_MANAGER_0_BRK_DELAY_RST_VALUE 0x00000000
#define XPAR_PSV_PMC_TMR_MANAGER_0_MASK_RST_VALUE 0xFFFFFFFFFFFFFFFF
#define XPAR_PSV_PMC_TMR_MANAGER_0_MAGIC1 0x00
#define XPAR_PSV_PMC_TMR_MANAGER_0_MAGIC2 0x00
#define XPAR_PSV_PMC_TMR_MANAGER_0_UE_IS_FATAL 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_UE_WIDTH 3
#define XPAR_PSV_PMC_TMR_MANAGER_0_NO_OF_COMPARATORS 1
#define XPAR_PSV_PMC_TMR_MANAGER_0_COMPARATORS_MASK 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_WATCHDOG 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_WATCHDOG_WIDTH 30
#define XPAR_PSV_PMC_TMR_MANAGER_0_SEM_INTERFACE 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG_WIDTH 10
#define XPAR_PSV_PMC_TMR_MANAGER_0_BRK_DELAY_WIDTH 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_TMR 1
#define XPAR_PSV_PMC_TMR_MANAGER_0_TEST_COMPARATOR 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_STRICT_MISCOMPARE 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_USE_DEBUG_DISABLE 0
#define XPAR_PSV_PMC_TMR_MANAGER_0_USE_TMR_DISABLE 0


/******************************************************************/

/* Canonical definitions for peripheral PSV_PMC_TMR_MANAGER_0 */
#define XPAR_TMR_MANAGER_0_DEVICE_ID XPAR_PSV_PMC_TMR_MANAGER_0_DEVICE_ID
#define XPAR_TMR_MANAGER_0_BASEADDR 0xF0283000
#define XPAR_TMR_MANAGER_0_HIGHADDR 0xF0283FFF
#define XPAR_TMR_MANAGER_0_BRK_DELAY_RST_VALUE 0x00000000
#define XPAR_TMR_MANAGER_0_MASK_RST_VALUE 0xFFFFFFFFFFFFFFFF
#define XPAR_TMR_MANAGER_0_MASK 0x0000000000083000
#define XPAR_TMR_MANAGER_0_MAGIC1 0x00
#define XPAR_TMR_MANAGER_0_MAGIC2 0x00
#define XPAR_TMR_MANAGER_0_UE_IS_FATAL 0
#define XPAR_TMR_MANAGER_0_UE_WIDTH 3
#define XPAR_TMR_MANAGER_0_NO_OF_COMPARATORS 1
#define XPAR_TMR_MANAGER_0_COMPARATORS_MASK 0
#define XPAR_TMR_MANAGER_0_WATCHDOG 0
#define XPAR_TMR_MANAGER_0_WATCHDOG_WIDTH 30
#define XPAR_TMR_MANAGER_0_SEM_INTERFACE 0
#define XPAR_TMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG 0
#define XPAR_TMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG_WIDTH 10
#define XPAR_TMR_MANAGER_0_BRK_DELAY_WIDTH 0
#define XPAR_TMR_MANAGER_0_TMR 1
#define XPAR_TMR_MANAGER_0_TEST_COMPARATOR 0
#define XPAR_TMR_MANAGER_0_STRICT_MISCOMPARE 0
#define XPAR_TMR_MANAGER_0_USE_DEBUG_DISABLE 0
#define XPAR_TMR_MANAGER_0_USE_TMR_DISABLE 0


/******************************************************************/

/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 3U

/* Definitions for peripheral PSV_TTC_0 */
#define XPAR_PSV_TTC_0_DEVICE_ID 0U
#define XPAR_PSV_TTC_0_BASEADDR 0XFF0E0000U
#define XPAR_PSV_TTC_0_TTC_CLK_FREQ_HZ 149999985U
#define XPAR_PSV_TTC_0_TTC_CLK_CLKSRC 0U
#define XPAR_PSV_TTC_1_DEVICE_ID 1U
#define XPAR_PSV_TTC_1_BASEADDR 0XFF0E0004U
#define XPAR_PSV_TTC_1_TTC_CLK_FREQ_HZ 149999985U
#define XPAR_PSV_TTC_1_TTC_CLK_CLKSRC 0U
#define XPAR_PSV_TTC_2_DEVICE_ID 2U
#define XPAR_PSV_TTC_2_BASEADDR 0XFF0E0008U
#define XPAR_PSV_TTC_2_TTC_CLK_FREQ_HZ 149999985U
#define XPAR_PSV_TTC_2_TTC_CLK_CLKSRC 0U


/******************************************************************/

/* Canonical definitions for peripheral PSV_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSV_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xFF0E0000U
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 149999985U
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSV_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xFF0E0004U
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 149999985U
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U

#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSV_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xFF0E0008U
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 149999985U
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U


/******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1U

/* Definitions for peripheral PSV_PMC_PPU1_MDM_0 */
#define XPAR_PSV_PMC_PPU1_MDM_0_DEVICE_ID 0U
#define XPAR_PSV_PMC_PPU1_MDM_0_BASEADDR 0xF0310000U
#define XPAR_PSV_PMC_PPU1_MDM_0_HIGHADDR 0xF0317FFFU
#define XPAR_PSV_PMC_PPU1_MDM_0_BAUDRATE 0U
#define XPAR_PSV_PMC_PPU1_MDM_0_USE_PARITY 0U
#define XPAR_PSV_PMC_PPU1_MDM_0_ODD_PARITY 0U
#define XPAR_PSV_PMC_PPU1_MDM_0_DATA_BITS 0U

/* Canonical definitions for peripheral PSV_PMC_PPU1_MDM_0 */
#define XPAR_UARTLITE_0_DEVICE_ID 0U
#define XPAR_UARTLITE_0_BASEADDR 0xF0310000U
#define XPAR_UARTLITE_0_HIGHADDR 0xF0317FFFU
#define XPAR_UARTLITE_0_BAUDRATE 0U
#define XPAR_UARTLITE_0_USE_PARITY 0U
#define XPAR_UARTLITE_0_ODD_PARITY 0U
#define XPAR_UARTLITE_0_DATA_BITS 0U


/******************************************************************/
/* Definitions for driver UARTPSV */
#define XPAR_XUARTPSV_NUM_INSTANCES 1

/* Definitions for peripheral PSV_SBSAUART_0 */
#define XPAR_PSV_SBSAUART_0_DEVICE_ID 0
#define XPAR_PSV_SBSAUART_0_BASEADDR 0xF1920000
#define XPAR_PSV_SBSAUART_0_HIGHADDR 0xF192FFFF
#define XPAR_PSV_SBSAUART_0_UART_CLK_FREQ_HZ 99999992
#define XPAR_PSV_SBSAUART_0_HAS_MODEM 0
#define XPAR_PSV_SBSAUART_0_BAUDRATE 115200


/******************************************************************/

/* Canonical definitions for peripheral PSV_SBSAUART_0 */
#define XPAR_XUARTPSV_0_DEVICE_ID XPAR_PSV_SBSAUART_0_DEVICE_ID
#define XPAR_XUARTPSV_0_BASEADDR 0xF1920000
#define XPAR_XUARTPSV_0_HIGHADDR 0xF192FFFF
#define XPAR_XUARTPSV_0_UART_CLK_FREQ_HZ 99999992
#define XPAR_XUARTPSV_0_HAS_MODEM 0


/******************************************************************/

/* Definitions for driver USBPSU */
#define XPAR_XUSBPSU_NUM_INSTANCES 1

/* Definitions for peripheral PSV_USB_XHCI_0 */
#define XPAR_PSV_USB_XHCI_0_DEVICE_ID 0
#define XPAR_PSV_USB_XHCI_0_BASEADDR 0xF1B00000
#define XPAR_PSV_USB_XHCI_0_HIGHADDR 0xF1BFFFFF


/******************************************************************/

#define XPAR_PSV_USB_XHCI_0_IS_CACHE_COHERENT 0
#define XPAR_PSV_USB_XHCI_0_SUPER_SPEED 0
/* Canonical definitions for peripheral PSV_USB_XHCI_0 */
#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSV_USB_XHCI_0_DEVICE_ID
#define XPAR_XUSBPSU_0_BASEADDR 0xF1B00000
#define XPAR_XUSBPSU_0_HIGHADDR 0xF1BFFFFF


/******************************************************************/

/* Definitions for driver ZDMA */
#define XPAR_XZDMA_NUM_INSTANCES 8

/* Definitions for peripheral PSV_ADMA_0 */
#define XPAR_PSV_ADMA_0_DEVICE_ID 0
#define XPAR_PSV_ADMA_0_BASEADDR 0xFFA80000
#define XPAR_PSV_ADMA_0_DMA_MODE 1
#define XPAR_PSV_ADMA_0_HIGHADDR 0xFFA8FFFF
#define XPAR_PSV_ADMA_0_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_1 */
#define XPAR_PSV_ADMA_1_DEVICE_ID 1
#define XPAR_PSV_ADMA_1_BASEADDR 0xFFA90000
#define XPAR_PSV_ADMA_1_DMA_MODE 1
#define XPAR_PSV_ADMA_1_HIGHADDR 0xFFA9FFFF
#define XPAR_PSV_ADMA_1_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_2 */
#define XPAR_PSV_ADMA_2_DEVICE_ID 2
#define XPAR_PSV_ADMA_2_BASEADDR 0xFFAA0000
#define XPAR_PSV_ADMA_2_DMA_MODE 1
#define XPAR_PSV_ADMA_2_HIGHADDR 0xFFAAFFFF
#define XPAR_PSV_ADMA_2_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_3 */
#define XPAR_PSV_ADMA_3_DEVICE_ID 3
#define XPAR_PSV_ADMA_3_BASEADDR 0xFFAB0000
#define XPAR_PSV_ADMA_3_DMA_MODE 1
#define XPAR_PSV_ADMA_3_HIGHADDR 0xFFABFFFF
#define XPAR_PSV_ADMA_3_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_4 */
#define XPAR_PSV_ADMA_4_DEVICE_ID 4
#define XPAR_PSV_ADMA_4_BASEADDR 0xFFAC0000
#define XPAR_PSV_ADMA_4_DMA_MODE 1
#define XPAR_PSV_ADMA_4_HIGHADDR 0xFFACFFFF
#define XPAR_PSV_ADMA_4_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_5 */
#define XPAR_PSV_ADMA_5_DEVICE_ID 5
#define XPAR_PSV_ADMA_5_BASEADDR 0xFFAD0000
#define XPAR_PSV_ADMA_5_DMA_MODE 1
#define XPAR_PSV_ADMA_5_HIGHADDR 0xFFADFFFF
#define XPAR_PSV_ADMA_5_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_6 */
#define XPAR_PSV_ADMA_6_DEVICE_ID 6
#define XPAR_PSV_ADMA_6_BASEADDR 0xFFAE0000
#define XPAR_PSV_ADMA_6_DMA_MODE 1
#define XPAR_PSV_ADMA_6_HIGHADDR 0xFFAEFFFF
#define XPAR_PSV_ADMA_6_ZDMA_CLK_FREQ_HZ 0


/* Definitions for peripheral PSV_ADMA_7 */
#define XPAR_PSV_ADMA_7_DEVICE_ID 7
#define XPAR_PSV_ADMA_7_BASEADDR 0xFFAF0000
#define XPAR_PSV_ADMA_7_DMA_MODE 1
#define XPAR_PSV_ADMA_7_HIGHADDR 0xFFAFFFFF
#define XPAR_PSV_ADMA_7_ZDMA_CLK_FREQ_HZ 0


/******************************************************************/

#define XPAR_PSV_ADMA_0_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_1_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_2_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_3_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_4_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_5_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_6_IS_CACHE_COHERENT 0
#define XPAR_PSV_ADMA_7_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PSV_ADMA_0 */
#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSV_ADMA_0_DEVICE_ID
#define XPAR_XZDMA_0_BASEADDR 0xFFA80000
#define XPAR_XZDMA_0_DMA_MODE 1
#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF
#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_1 */
#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSV_ADMA_1_DEVICE_ID
#define XPAR_XZDMA_1_BASEADDR 0xFFA90000
#define XPAR_XZDMA_1_DMA_MODE 1
#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF
#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_2 */
#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSV_ADMA_2_DEVICE_ID
#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000
#define XPAR_XZDMA_2_DMA_MODE 1
#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF
#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_3 */
#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSV_ADMA_3_DEVICE_ID
#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000
#define XPAR_XZDMA_3_DMA_MODE 1
#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF
#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_4 */
#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSV_ADMA_4_DEVICE_ID
#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000
#define XPAR_XZDMA_4_DMA_MODE 1
#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF
#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_5 */
#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSV_ADMA_5_DEVICE_ID
#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000
#define XPAR_XZDMA_5_DMA_MODE 1
#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF
#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_6 */
#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSV_ADMA_6_DEVICE_ID
#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000
#define XPAR_XZDMA_6_DMA_MODE 1
#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF
#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0

/* Canonical definitions for peripheral PSV_ADMA_7 */
#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSV_ADMA_7_DEVICE_ID
#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000
#define XPAR_XZDMA_7_DMA_MODE 1
#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF
#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0


/******************************************************************/

/* Xilinx FAT File System Library (XilFFs) User Settings */
#define FILE_SYSTEM_INTERFACE_SD
#define FILE_SYSTEM_READ_ONLY
#define FILE_SYSTEM_MULTI_PARTITION
#define FILE_SYSTEM_NUM_LOGIC_VOL 10
#define FILE_SYSTEM_USE_STRFUNC 0
#define FILE_SYSTEM_SET_FS_RPATH 0

/* PLM/XilPLMI configuration */

/* Debug level option */
#define PLM_DEBUG

/* Boot time measurement enable */
#define PLM_PRINT_PERF

/* USB Boot mode support disable */
#define PLM_USB_EXCLUDE

/* NVM handlers disable */
#define PLM_NVM_EXCLUDE

/* PUF handlers disable */
#define PLM_PUF_EXCLUDE

#define XPAR_XILPM_ENABLED

/* Xilinx Secure library ecdsa endianness Settings */
#define XSECURE_ELLIPTIC_ENDIANNESS	0U	/* 0: Little Endian and 1: Big endian */
#endif  /* end of protection macro */
